paper 5.2 Using Transition Test to Understand Timing Behavior of Logic Circuits on UltraSPARCTM T2 Family

ABSTRACT

1. Introduction
Speed is vitally important in microprocessor design
and test

There are four classes of tests used to characterize the
speed of a chip: functional, BIST, path delay, and transition
delay.

The work done in this paper was part of the bring-up
effort for the UltraSPARC T2 microprocessor

(page 2)
The structure of this paper is as follows.

2. Previous Work
Speed comparison was performed between functional
test and at-speed structural tests (memory BIST,
transition test (TT), and path-delay test (PDT)) on 633
chips in [3].

page 2 col 2
A transition test flow was developed in [9], including
test generation, silicon bring-up, and timing characterization/
diagnosis.

Wire-dominated paths usually have a large interconnect
delay, which was projected to increase significantly
in deep sub-micron design [10].

On gate-dominated paths, the excited path delay may
be larger than pin-to-pin delay along the same path,
when some side-inputs are also switching.

3. UltraSPARC T2/T2+ Chips
UltraSPARC T2 [15][6] is Sun Microsystems’ second
generation chip multi-threaded (CMT) processor in
the Eco-sensitive CoolThreadsTM line of multi-threaded
servers. It consists of eight 64-bit SPARCTM processor
cores, each supporting eight threads. It doubles the
number of per-core threads and incorporates a dedicated
floating point and graphics unit on each core to gain 8x
performance over the previous generation UltraSPARC
T1. T2, fabricated with 65nm triple-Vt CMOS process,
has 503M transistors and die size of 342mm2. UltraSPARC
T2+ is a follow-on to the UltraSPARC T2. T2+
shares the same core design with T2 and supports up to
a four-way coherent system.

p3

paper 5.1 AutoRex: An Automated Post-Silicon Clock Tuning Tool

Abstract

Post-silicon clock-tuning

I. Introduction
(page 2)

(page 3)
II. Formulating Timing Constraints For a Single Chip
We begin this section by deriving the constraint equation
for a simple case of one single critical path

Assume that clock-tuning buffers (CTBs) drive the final
source and destination clock signals for any speed path.

(page 4 col 2)

(page 6)
Another important set of real-world issues occurs when
the constraint set has multiple solutions

Consider the scenario where a chip has two independent
paths (A and B), and path A is longer than path B by
150 time units.

Instead, we would prefer to avoid adjusting the CTBs
of any paths that do not factor in setting the frequency of
the chip.

Consider another related scenario, where we have only
one path in a chip that needs to be improved by 25
time units

Unfortunately, our heuristic of maximizing the number
of CTBs that are set to 0 time units does not work for this
scenario.

Another real-world issue that can be included is holdtime
constraints.

III. Constraints For Multiple Chips
So far we have constructed constraints for paths on
one chip.

(page 7)

IV. Satisfiability Modulo Theory (SMT)

V. Algorithm
A. Optimization Using Decision Problems
B. Methodology

paper 4.3 Capture Power Reduction Using Clock Gating Aware Test Generation

Abstract
Scan-based manufacturing test of low power designs often exceeds the very tight functional constraints on average and instantaneous logic switching.

This paper focuses on the management of instantaneous power during the capture phase. (comment: the scope)

1. Introduction
Test mode power can exceed the functional power specifications for several reasons cited below.

Delay tests that utilize “Launch off capture” transition approaches can cause voltage drop due to inductive effects as two high speed clock pulses follow a quiescent period.

[6] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A gated clock scheme for low power scan testing of logic ICs or embedded cores,” Proc. Asian Test Symposium, 2001, pp. 253-258.

2. Previous Work
The proposed solution to these problems is to limit the clock activity in the capture cycles by imposing ATPG constraints on the enable signals of the clock gates.

3. Analysis of Capture Activity

(page 3)

4. Clock Gating ATPG Methodology

4.1. Locating Clock Gates in the Design
Synthesis support for clock gate insertion has become very sophisticated and current designs may contain within them coarse and/or fine grain clock gating as shown in Figure 6.

The process of identifying clock gates involves tracing back from the clock pin on each flop in the design. As each clock gate is encountered during such structural tracing, information is stored about the number of flops controlled by that clock gate.

5. Experimental Results

(page 7)

6. Ordering the Clock Gates

paper 4.2 Accurate Measurement of Small Delay Defect Coverage of Test Patterns

Abstract
1. Introduction
2. Prior Work
2.1 Delay Test Coverage Metric
2.1.1 Shortcomings of DTC Metric
2.2 Statistical Delay Quality Level Metric
2.2.1 Shortcomings of SDQL Metric
(page 5)
3. Proposed SDD Test Coverage Metric
3.1 Quadratic SDD Test Coverage Metric
3.2 Faster-Than-At-Speed Testing
4. Experimental Results
4.1 Sensitivity to System Frequency
4.2 Sensitivity to Defect Distribution
4.3 Timing-Aware vs. Faster-Than-At-Speed
5. Conclusion

paper 4.1 Minimizing Outlier Delay Test Cost in the Presence of Systematic Variability

Abstract
I. INTRODUCTION
II. RELATED WORK
III. SVM OUTLIER ANALYSIS
A. Delay-Test Signature
B. Similarity Measures
C. One-Class Unsupervised Learning
D. Yield Parameter Selection
IV. EXPERIMENTAL SETUP
A. Setup Overview
B. Baseline Experiments
C. Cost Reduction
V. TEST COST MINIMIZATION
A. Minimizing Samples and Patterns
B. Entropy Measure
C. Single Clock Selection
D. Three Clock Selection
VI. METHODOLOGY
A. Preparation Phase
B. Application Phase
C. Implementation Practicality
VII. BENEFITS AND LIMITATIONS OF OUTLIER ANALYSIS
VIII. SUMMARY OF KEY FINDINGS
IX. CONCLUSION

paper 2.4 Boundary-Scan Adoption – An Industry Snapshot with Emphasis on the Semiconductor Industry

Abstract
1. Introduction
2. The iNEMI Boundary-Scan Survey
2.1 Survey Objectives
2.2 Survey Methodology
3. Boundary-Scan Survey Results
3.1 Respondent Statistics
3.1.1 Board/System Test Engineering Respondent Demographics
3.1.2 Semiconductor Engineering Demographics
3.2 Boundary-Scan Standards and Initiative Knowledge and Support
3.2.1 Board/System Test Engineering Support for Boundary-Scan Standards and Initiatives
3.2.2 Semiconductor Engineering Support for Boundary-Scan Standards and Initiatives
3.3 Board/System Engineering Survey Results
3.3.1 How Important is Boundary-Scan to Board/System Test Engineers?
3.3.2 How Does Boundary-Scan Affect Product Development Time and Cost?
3.3.3 Using Boundary-Scan to Test Non-Boundary-Scan Devices
3.3.4 Verifying Semiconductor JTAG Compliance
3.3.5 Issues Encountered When Implementing Boundary-Scan
3.3.6 Attributes Important to Board/System Engineers When Choosing a Semiconductor Supplier
3.4 Semiconductor Engineering Survey Results
3.4.1 Current and Planned Support for Boundary-Scan in Semiconductor Devices
3.4.2 Factors Hindering Successful Implementation of Boundary-Scan in IC Designs
3.4.3 Target Applications for Semiconductor Designs
3.4.4 Boundary-Scan Compliance in Semiconductors
3.4.5 Boundary-Scan Verification in Semiconductors
3.4.6 Availability and Use of Extended Test Functions in Semiconductors
3.4.7 BSDL Files and Confidentiality

paper 2.3 Fast Extended Test Access via JTAG and FPGAs

Abstract
1. Introduction
2. State-of-the-Art in Boundary Scan
2.1 Test access via Boundary Scan
2.2 Boundary Scan speed considerations
2.3 Testing dynamic devices
3. FPGA-based TAM Extension
3.1 Alternative test data transport options
4. Experimental results

Paper 2.2 Intel®IBIST. the Full Vision Realized

Abstract
I. INTRODUCTION
II. RELATED WORK AND MOTIVATION
III. ARCHITECTURE OF IMPLEMENTATION
IV. ARCHITECTURE OVERVIEW
B. IBIST Registers and Register Organization
C. IBIST Test Execution Control
D. Programming Model
E. Application Auto-discovery
F Pattern Generation and Error Checking
G. Electrical Margining
H. Link State Machine Debug Support
V. ApPLICATIONS
A. Validation
B. Manufacturing
C. RAS
D. Remote Diagnostics
VI. EXPERIMENTAL RESULTS
VII. SUMMARY & CONCLUSIONS

paper 2.1 Testing Bridges to Nowhere - Combining Boundary Scan and Capacitive Sensing

Abstract
1 Introduction
2 Capacitive Opens Test Background
3 Possible solutions, and challenges
3.1 IEEE 1149.1 Boundary Scan
3.2 1149.4 Mixed-Signal Test Bus
3.3 1149.6 Boundary Scan for Advanced I/O
3.4 Make Input-Only Pins Bi-Directional
3.5 Differential pins
3.6 Detecting Pull-up Resistors
3.7 Detecting Shorts on High-Drive Outputs
4 Details of the Proposed Boundary Scan
4.1 Not all signal pins
4.2 Toggle during Run-Test/Idle
4.3 All ST pins can drive out during ST mode
4.4 Update latch holds non-toggling pin value
4.5 Logic 1 in BSR selects toggling pins
4.6 Global toggling signal
4.7 Global ST-mode signal
4.8 Output drive
4.9 Differential outputs
5 Other capabilities of the infrastructure
5.1 Detecting pull-up resistance
5.2 Detecting shorts on high-drive outputs
6 Results
6.1 Coverage increases and/or access reductions
7 Limitations
8 Discussion

paper 1.4 Application of Non-parametric Statistics of the Parametric Response for Defect Diagnosis

Abstract
I. INTRODUCTION
II. ORDINAL INVARIANT AND RANK STATISTICS
The statistics calculated using rank order are called ordinal invariant statistics.
A. Kendall τ
III. IDDQ DEPENDENCE ON EXTRINSIC VARIABLES
ProdA data is from several lots totaling approximately 2,500 die.
IV. CORRELATION MODEL FOR IDDQ
A. True Value, TV
B. Process Noise, PN
For IDDQ process noise is dominated by sub-threshold current which is controlled by the temperature and threshold voltage.
C. Tester Noise
D. IDDQ Discordant Plots
V. MONTE-CARLO ESTIMATION
A. Shape (Homogeneity) of τ Extreme Values
B. Critical Value Tables
C. Effectiveness of Kendall τ
VI. KENDALL τ CONTRIBUTION TO DIAGNOSIS
A. Elevated versus Non-Elevated Vectors
VII. RESULTS
A. Outlier Screening
B. Elevated and Non-Elevated Vector Selection
C. Inter-Die Correlation
VIII. CONCLUSION

Paper 1.3 Test Effectiveness Evaluation through Analysis of Readily-Available Tester Data

1. Introduction
2. Test-Metric Evaluation using Diagnostics
2.1. Failing Chip Selection
2.2. Test Metric Evaluation
2.2.1. Bridge Fault Models
2.2.2. Gate-Exhaustive Metric
2.2.3. Physically-Aware N-Detect Test
3. Experiment
3.1. Single Suspect Failing Chips
3.2. Multiple Suspect Failing Chips
4. Discussion
4.1. Comparison of the Evaluated Test Metrics
4.2. Generalizing Test Metric Evaluation
4.3. Failing Chip Selection
4.4. Utilization of All Failing Patterns
4.5. Comparing Test Metric Evaluation Methods

Paper 1.2 Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs

[Abstract]
Industry is facing increasingly tougher quality requirements for more complex ICs.

The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults.

[1 Introduction]
To achieve today’s quality requirements on large Systems-on-Chips (SoC) we need to obtain high defect coverages with our test patterns.

[2 Previous Work]
[3.4 Cell-Aware Pattern Generation and Fault Simulation]