Paper 1.2 Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs

[Abstract]
Industry is facing increasingly tougher quality requirements for more complex ICs.

The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults.

[1 Introduction]
To achieve today’s quality requirements on large Systems-on-Chips (SoC) we need to obtain high defect coverages with our test patterns.

[2 Previous Work]
[3.4 Cell-Aware Pattern Generation and Fault Simulation]