paper 4.3 Capture Power Reduction Using Clock Gating Aware Test Generation

Abstract
Scan-based manufacturing test of low power designs often exceeds the very tight functional constraints on average and instantaneous logic switching.

This paper focuses on the management of instantaneous power during the capture phase. (comment: the scope)

1. Introduction
Test mode power can exceed the functional power specifications for several reasons cited below.

Delay tests that utilize “Launch off capture” transition approaches can cause voltage drop due to inductive effects as two high speed clock pulses follow a quiescent period.

[6] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A gated clock scheme for low power scan testing of logic ICs or embedded cores,” Proc. Asian Test Symposium, 2001, pp. 253-258.

2. Previous Work
The proposed solution to these problems is to limit the clock activity in the capture cycles by imposing ATPG constraints on the enable signals of the clock gates.

3. Analysis of Capture Activity

(page 3)

4. Clock Gating ATPG Methodology

4.1. Locating Clock Gates in the Design
Synthesis support for clock gate insertion has become very sophisticated and current designs may contain within them coarse and/or fine grain clock gating as shown in Figure 6.

The process of identifying clock gates involves tracing back from the clock pin on each flop in the design. As each clock gate is encountered during such structural tracing, information is stored about the number of flops controlled by that clock gate.

5. Experimental Results

(page 7)

6. Ordering the Clock Gates