paper 5.1 AutoRex: An Automated Post-Silicon Clock Tuning Tool

Abstract

Post-silicon clock-tuning

I. Introduction
(page 2)

(page 3)
II. Formulating Timing Constraints For a Single Chip
We begin this section by deriving the constraint equation
for a simple case of one single critical path

Assume that clock-tuning buffers (CTBs) drive the final
source and destination clock signals for any speed path.

(page 4 col 2)

(page 6)
Another important set of real-world issues occurs when
the constraint set has multiple solutions

Consider the scenario where a chip has two independent
paths (A and B), and path A is longer than path B by
150 time units.

Instead, we would prefer to avoid adjusting the CTBs
of any paths that do not factor in setting the frequency of
the chip.

Consider another related scenario, where we have only
one path in a chip that needs to be improved by 25
time units

Unfortunately, our heuristic of maximizing the number
of CTBs that are set to 0 time units does not work for this
scenario.

Another real-world issue that can be included is holdtime
constraints.

III. Constraints For Multiple Chips
So far we have constructed constraints for paths on
one chip.

(page 7)

IV. Satisfiability Modulo Theory (SMT)

V. Algorithm
A. Optimization Using Decision Problems
B. Methodology