paper 2.1 Testing Bridges to Nowhere - Combining Boundary Scan and Capacitive Sensing

Abstract
1 Introduction
2 Capacitive Opens Test Background
3 Possible solutions, and challenges
3.1 IEEE 1149.1 Boundary Scan
3.2 1149.4 Mixed-Signal Test Bus
3.3 1149.6 Boundary Scan for Advanced I/O
3.4 Make Input-Only Pins Bi-Directional
3.5 Differential pins
3.6 Detecting Pull-up Resistors
3.7 Detecting Shorts on High-Drive Outputs
4 Details of the Proposed Boundary Scan
4.1 Not all signal pins
4.2 Toggle during Run-Test/Idle
4.3 All ST pins can drive out during ST mode
4.4 Update latch holds non-toggling pin value
4.5 Logic 1 in BSR selects toggling pins
4.6 Global toggling signal
4.7 Global ST-mode signal
4.8 Output drive
4.9 Differential outputs
5 Other capabilities of the infrastructure
5.1 Detecting pull-up resistance
5.2 Detecting shorts on high-drive outputs
6 Results
6.1 Coverage increases and/or access reductions
7 Limitations
8 Discussion

paper 1.4 Application of Non-parametric Statistics of the Parametric Response for Defect Diagnosis

Abstract
I. INTRODUCTION
II. ORDINAL INVARIANT AND RANK STATISTICS
The statistics calculated using rank order are called ordinal invariant statistics.
A. Kendall τ
III. IDDQ DEPENDENCE ON EXTRINSIC VARIABLES
ProdA data is from several lots totaling approximately 2,500 die.
IV. CORRELATION MODEL FOR IDDQ
A. True Value, TV
B. Process Noise, PN
For IDDQ process noise is dominated by sub-threshold current which is controlled by the temperature and threshold voltage.
C. Tester Noise
D. IDDQ Discordant Plots
V. MONTE-CARLO ESTIMATION
A. Shape (Homogeneity) of τ Extreme Values
B. Critical Value Tables
C. Effectiveness of Kendall τ
VI. KENDALL τ CONTRIBUTION TO DIAGNOSIS
A. Elevated versus Non-Elevated Vectors
VII. RESULTS
A. Outlier Screening
B. Elevated and Non-Elevated Vector Selection
C. Inter-Die Correlation
VIII. CONCLUSION

Paper 1.3 Test Effectiveness Evaluation through Analysis of Readily-Available Tester Data

1. Introduction
2. Test-Metric Evaluation using Diagnostics
2.1. Failing Chip Selection
2.2. Test Metric Evaluation
2.2.1. Bridge Fault Models
2.2.2. Gate-Exhaustive Metric
2.2.3. Physically-Aware N-Detect Test
3. Experiment
3.1. Single Suspect Failing Chips
3.2. Multiple Suspect Failing Chips
4. Discussion
4.1. Comparison of the Evaluated Test Metrics
4.2. Generalizing Test Metric Evaluation
4.3. Failing Chip Selection
4.4. Utilization of All Failing Patterns
4.5. Comparing Test Metric Evaluation Methods

Paper 1.2 Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs

[Abstract]
Industry is facing increasingly tougher quality requirements for more complex ICs.

The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults.

[1 Introduction]
To achieve today’s quality requirements on large Systems-on-Chips (SoC) we need to obtain high defect coverages with our test patterns.

[2 Previous Work]
[3.4 Cell-Aware Pattern Generation and Fault Simulation]