ABSTRACT
1. Introduction
Speed is vitally important in microprocessor design
and test
There are four classes of tests used to characterize the
speed of a chip: functional, BIST, path delay, and transition
delay.
The work done in this paper was part of the bring-up
effort for the UltraSPARC T2 microprocessor
(page 2)
The structure of this paper is as follows.
2. Previous Work
Speed comparison was performed between functional
test and at-speed structural tests (memory BIST,
transition test (TT), and path-delay test (PDT)) on 633
chips in [3].
page 2 col 2
A transition test flow was developed in [9], including
test generation, silicon bring-up, and timing characterization/
diagnosis.
Wire-dominated paths usually have a large interconnect
delay, which was projected to increase significantly
in deep sub-micron design [10].
On gate-dominated paths, the excited path delay may
be larger than pin-to-pin delay along the same path,
when some side-inputs are also switching.
3. UltraSPARC T2/T2+ Chips
UltraSPARC T2 [15][6] is Sun Microsystems’ second
generation chip multi-threaded (CMT) processor in
the Eco-sensitive CoolThreadsTM line of multi-threaded
servers. It consists of eight 64-bit SPARCTM processor
cores, each supporting eight threads. It doubles the
number of per-core threads and incorporates a dedicated
floating point and graphics unit on each core to gain 8x
performance over the previous generation UltraSPARC
T1. T2, fabricated with 65nm triple-Vt CMOS process,
has 503M transistors and die size of 342mm2. UltraSPARC
T2+ is a follow-on to the UltraSPARC T2. T2+
shares the same core design with T2 and supports up to
a four-way coherent system.
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